Implantable biomedical devices have been developed for different applications such as retinal prosthesis, cochlear implant, and arm rehabilitation.
As an example, “A 232-channel epiretinal stimulator ASIC,” by M. Ortmanns et al., IEEE Journal of Solid-State Circuits, Vol. 42, pp. 2946-2959, December 2007, which is incorporated herein by reference in its entirety, describes implantable biomedical devices developed for retinal prosthesis. Other examples include: “A 32-Site 4-Channel Cochlear Electrode Array,” by P. Bhatti et al., ISSCC Dig. Tech. Papers, pp. 50-51, February 2006, which is incorporated herein by reference in its entirety, describes implantable biomedical devices developed for cochlear implants and “A Biomedical Implantable FES Battery-Powered Micro-Stimulator,” by E. Matei et al., Proc. IEEE 2008 CICC, pp. 317-324, September 2008, which is incorporated herein by reference in its entirety, describes implantable biomedical devices developed for arm rehabilitation.
Implantable biomedical devices are usually powered by inductive coupling directly from a radio frequency (RF) field or from a rechargeable battery that is recharged by means of inductive coupling with an external RF field.
FIG. 1 shows an exemplary implementation of an inductively powered implantable medical device (100) used in both the case of implantable biomedical devices powered by inductive coupling from an RF field directly as well as from a rechargeable battery managed by a battery management unit. As shown in FIG. 1, a primary voltage V1 (105) from a first coil LS (110) induces a voltage V2 (115) in a second coil L (120). More specifically, the coil L (120) located inside the implantable device (100) receives power by means of magnetic coupling from an external magnetic field generator (125). In general, overall power consumption for most implantable biomedical devices (100) is relatively low, usually not exceeding tens of milliwatts.
The induced voltage V2 (115) is rectified and converted to a DC voltage VDC (130) by a rectifier (135). The DC voltage VDC (130) is used for powering circuits in the implantable device (100) directly or for recharging a battery in the implantable device (100). Peak to peak induced voltage V2 (115), denoted as V2Pk-Pk, depends on a number of factors such as:                (a) design of coil LS (110) and coil L (120) including the turns ratio,        (b) equivalent load seen by the circuit comprising coil L (115) and a tuning capacitor C (140),        (c) magnitude of the external magnetic field provided by generator (125), and        (d) distance between and orientation of coil LS (110) and coil L (120).The peak to peak voltage V2Pk-Pk of the induced voltage V2 (115) can range from a few volts to around 20 V.        
In the following figures, NMOSs and PMOSs will be used in exemplary implementations of circuit devices. The NMOS has a threshold voltage denoted as VTN and the PMOS has a threshold voltage denoted as VTP. A typical value for the threshold voltages is 0.5 volts for an exemplary 0.18 um CMOS process.
FIGS. 2A and 2B show two exemplary implementations of conventional CMOS full wave rectifier circuits and it is instructive to discuss operation of these circuits in detail in order to gain a better understanding of the novel advancement the current invention provides over the present state of the art.
FIG. 2A shows a first implementation of a conventional CMOS full wave rectifier circuit (200). The implementation in FIG. 2A comprises a first NMOS field effect transistor (FET) M1 (205), a second NMOS FET M2 (210), a first diode connected PMOS FET M3 (215), and a second diode connected PMOS FET M4 (220). A diode connected FET is referred to in a configuration when a FET gate and drain are connected together so that the FET functions as a diode. The drain of the first NMOS FET M1 (205) is connected to the source of the first PMOS FET M3 (215) and the drain of the second NMOS FET M2 (210) is connected to the source of the second PMOS FET M4 (220). The two NMOS FETs M1 (205) and M2 (210) are connected together in what is referred to as a cross coupled arrangement. In particular, the gate of the first NMOS FET M1 (205) is connected to the drain of the second NMOS FET M2 (210) and the gate of the second NMOS FET M2 (210) is connected to the drain of the first NMOS FET M1 (205).
An induced voltage V2 (202) is a difference between voltage VR1 (225) appearing at node NR1 (226) and voltage VR2 (230) appearing at node NR2 (231), namely V2=VR1−VR2. When NMOS FET M1 (205) is conducting (or “ON”), node NR1 (226) is connected to ground (235). Similarly, when NMOS FET M2 (210) is conducting, node NR2 (231) is connected to ground (235). Voltages 225 or 230, at nodes 226 or 231 respectively, are applied to output node NOUT (241) by means of diode connected PMOS FET (215 or 220) and supply an output current IOUT (242) to a load circuit (not shown).
Operation of the circuit of FIG. 2A is as follows: consider a case when the induced voltage V2 (202) is at a peak value V2P with the voltage VR1 (225) at its maximum value and the voltage VR2 (230) at its minimum value.
The second NMOS FET M2 (210) has the voltage VR2 (230) applied to its drain, the voltage VR1 (225) applied to its gate, and the ground terminal (235) tied to its source. The second NMOS FET M2 (210) operates in the triode mode since VGS2=VR1>VTN and VGD2=VR1−VR2>VTN, where VGS2 is the gate-to-source voltage of the NMOS FET M2 (205) and VGD2 is the gate to drain voltage of the NMOS FET M2 (210) The second NMOS FET M2 (210) is turned on (conductive) and node NR2 (231) is tied to the ground terminal (235). Therefore, current flows from node NR2 (231) to the ground terminal (235).
The first NMOS FET M1 (205) has the voltage VR1 (225) applied to its drain, the voltage VR2 (230) applied to its gate, and the ground terminal (235) tied to its source. The first NMOS FET M1 (205) operates in cutoff mode because VGS1=VR2<VTN, where VGS1 is the gate-to-source voltage of the NMOS FET M1 (205). Therefore, no significant current flows through the NMOS FET M1 (205).
The voltage VR1 (225) appearing at NR1 (226) is sufficiently large so as to turn on the diode connected PMOS FET M3 (215). The node NR1 (226) is tied to output node NOUT (241), and thus the voltage VR1 (225) minus a voltage drop typically in the range of 0.5 to 1.0 volts due to the diode connected PMOS FET M3 (215) is applied to the load circuit (not shown). The voltage VR1 (225) minus a voltage drop due to the diode connected PMOS FET M3 (215) is denoted as an output voltage VDD (240) in FIG. 2A.
A similar case exists when the voltage VR2 (230) is at a maximum value and the voltage VR1 (225) is at a minimum value. The first NMOS FET M1 (205) operates in a triode mode and thus node NR1 (226) is tied to the ground terminal (235). The second NMOS FET M2 (210) operates in cutoff mode. The voltage VR2 (230) turns on the diode connected PMOS FET M4 (220), and thus the voltage VR2 (230) minus a voltage drop due to the diode connected PMOS FET M4 (220) is applied to the load circuit (not shown). In this case, the output voltage VDD (240) in FIG. 2A is the voltage VR2 (230) minus a voltage drop due to the diode connected PMOS FET M4 (220).
A technical paper entitled “Fully Integrated Wideband High-Current Rectifiers for Inductively Powered Devices,” by M. Ghovanloo and K. Najafi, IEEE Journal of Solid-State Circuits, Vol. 39, No. 11, pp. 1976-1984, November 2004, which is incorporated herein by reference in its entirety, proposes a technique to prevent a latch-up condition due to parasitic bipolar transistors associated with the PMOS FETs (215, 220).
FIG. 2B shows a second implementation (250) of a conventional CMOS full wave rectifier. The implementation in FIG. 2B comprises a first PMOS FET M1 (255), a second PMOS FET M2 (260) in a cross coupled arrangement, a first diode DNS1 (265), and a second diode DNS2 (270). In particular, the gate of the first PMOS FET M1 (255) is connected to the drain of the second PMOS FET M2 (260) and the gate of the second PMOS FET M2 (260) is connected to the drain of the first PMOS FET M1 (255). The bulk terminals of the PMOS FETs (255, 260) are connected to the output voltage VDD (240).
The diodes DNS1 (265) and DNS2 (270) connect either node NR1 (226), at which voltage VR1 (225) appears, or node NR2 (231), at which voltage VR2 (230) appears, to the ground terminal (235). The voltage 225 or 230 is applied to the load circuit (not shown) and supplies the output current IOUT (242) through the corresponding PMOS FETs 255 or 260.
The following analysis is similar to that given in relation to FIG. 2A. The first diode DNS1 (265) has the voltage VR1 (225) applied to its cathode and the ground terminal (235) tied to its anode. The second diode DNS2 (270) has the voltage VR2 (230) applied to its cathode and the ground terminal (235) tied to its anode.
Consider a case when the induced voltage V2 (202) is at the peak value V2P with the voltage VR1 (225) at its maximum value and the voltage VR2 (230) at its minimum value. Diode DNS1 (265) is reverse biased since its cathode is positive relative to its anode. The diode DNS2 (270) is forward biased since its cathode is negative relative to its anode. The node NR2 (231) is thus tied to the ground terminal (235). Consequently, current flows from node NR2 (231) to the ground terminal (235) whereas no significant current flows from node NR1 (226) to the ground terminal (235).
The second PMOS FET M2 (260) has the voltage VR2 (230) applied to its drain, the voltage VR1 (225) applied to its gate, and the output node NOUT (241) tied to its source. The second PMOS FET M2 (260) operates in cutoff mode because VGS2=VR1−VDD>VTP, where VGS2 is the gate-to-source voltage of the PMOS FET M2 (260). Consequently, no current flows from the second node NR2 (231) to the output node NOUT (241).
The first PMOS FET M1 (255) has the voltage VR1 (225) applied to its drain, the voltage VR2 (230) applied to its gate, and the output node NOUT (241) tied to its source. The first PMOS FET M1 (255) operates in triode mode because VGS1=VR2−VDD<VTP and VDG1=VR1−VR2>|VTP|, where VGS1 is the gate-to-source voltage of the PMOS M1 (255) and VDG1 is the drain-to-gate voltage of the PMOS FET M1 (255). Consequently, the first PMOS FET M1 (255) is turned on and node NR1 (231) is tied to output node NOUT (241). As a result, current flows from node NR1 (226) through the first PMOS FET M1 (255) to the output node NOUT (241). The voltage VR1 (225) minus a small voltage drop due to the diode DNS2 (270) is applied to the load circuit (not shown). This small voltage drop is typically in the range of tens of mV and can be neglected typically for a large width-length ratio for the PMOS FET M1 (255). The voltage VR1 (225) minus a voltage drop due to the diode DNS1 (265) is denoted as the output voltage VDD (240) in FIG. 2B.
A similar case exists when the voltage VR2 (230) is at a maximum value and the voltage VR1 (225) is at a minimum value. The first diode DNS1 (265) is forward biased and thus ties the first node NR1 (226) to the ground terminal (235) and the second diode DNS2 (270) is reverse biased. The voltage VR2 (230) turns on the PMOS FET M2 (260), and thus the voltage VR2 (230) minus a voltage drop due to the PMOS FET M2 (260) is applied to the load circuit (not shown). In this case, the output voltage VDD (240) in FIG. 2A is the voltage VR2 (230) minus a voltage drop due to the PMOS FET M2 (260).
For both conventional rectifiers shown in FIGS. 2A and 2B, the voltages across different terminals of the PMOS FETs and/or NMOS FETs will typically see the full swing of the induced voltage. Therefore, the breakdown voltages or the voltage limits of these FETs (typically in the range of ˜3.6V for a conventional 0.18 μm CMOS process) have to be higher than the peak induced voltage such that stress conditions will not occur on these FETs. As a result, an induced voltage with large peak value (>˜3.6V) cannot be applied on these conventional rectifiers.